1. Field of the Invention
The present invention generally relates to a semiconductor device, and particularly relates to a semiconductor device utilizing a flexible insulating substrate as a semiconductor chip mounting board and a method of manufacturing such a semiconductor device.
2. Description of the Related Art
Recently, there is a need for a semiconductor device having a high density, a high processing speed and a high-power structure. Also, there is a need for a semiconductor device having a package structure which can be obtained with a comparatively low cost.
In order to satisfy the needs above, fine-pitched package structures such as an FBGA (Fine Pitch Ball Grid Array) type structure have been developed and are now being used in various electronic devices. Among such FBGA-type packages, a package structure which uses a tape-type package for achieving a further fine-pitched structure is now becoming of a greater interest.
FIG. 1 is a partial cross-sectional view of a semiconductor device 1 of an FBGA-type of the related art. The semiconductor device 1 includes a tape 2, a semiconductor chip 4, solder balls 6 and a sealing resin 8.
The tape 2 is, for example, made of a polyimide resin. As shown in FIG. 2, a front surface 2a of the tape 2 is provided with electrode patterns 10 and bonding pads 12 formed thereon. Further, the front surface 2a of the tape 2 is provided with the semiconductor chip 4 mounted thereon. The electrode patterns 10 and the bonding pads 12 are formed on the tape 2 by, first, providing a copper layer on the tape 2 and then forming predetermined patterns, for example, by etching. Also, the electrode patterns 10 and the bonding pads 12 are electrically connected via interconnection patterns 13.
As shown in FIG. 3, wires 14 are provided between electrode pads 5 formed on a semiconductor chip 4 and bonding pads 12, respectively. Thus, the semiconductor chip 4 and the electrode patterns 10 are electrically connected via the wires 14, the bonding pads 12 and the interconnection patterns 13.
Further, the tape 2 is provided with holes 16 passing through the tape 2 at positions corresponding to the electrode patterns 10. The holes 16 may be formed by implementing a laser treatment on the tape 2.
A back surface 2b of the tape 2 is provided with solder balls 6 provided thereon. The solder balls 6 are provided at positions corresponding to the above-described holes 16 and are joined to the electrode patterns 10 via the holes 16. In other words, the solder balls 6 are fixed on the tape 2 by being joined to the electrode patterns 10.
The solder balls 6 may be joined to the electrode patterns 10 in the following manner. First, the tape 2 provided with the electrode patterns 10 and the holes 16 is reversed, so that the spherical solder balls 6 are placed above the holes 16. Then, a heating treatment is implemented so that the solder balls 6 are fused and a part of each of the solder balls 6 flows into a corresponding one of the holes 16.
Subsequently, a cooling treatment is implemented so as to cure the solder and fix the solder balls 6 to the electrode patterns 10. The solder balls 6 are joined to the electrode patterns 10 by implementing the above-described treatments. A part of the solder ball 6 protruding from the hole 16 is formed into a spherical shape due to the surface tension resulting from the fusion of the solder.
With the above-described semiconductor device 1 of an FBGA-type structure utilizing the tape 2 as a substrate, the solder balls 6 can be provided at a finer pitch. Therefore, it is possible to obtain a high-density semiconductor chip 4 and a reduced-sized semiconductor.
Now, the semiconductor device I of an FBGA type of the related art will be described in detail in regards to positioning of the electrode patterns 10 and the bonding pads 12.
Generally, the solder balls 6 are provided in a grid shape. In the embodiment shown in FIGS. 1 to 3, four rows of solder balls 6 are provided on the tape with an outermost row being referred to as Row No. 1. Therefore, the electrode patterns 10 corresponding to the positions of the solder balls 6 are also provided in four rows in a grid shape.
On the other hand, in the prior art, the bonding pads 12 whereto the wires 14 are to be connected have always been formed in a single row irrespective of the number of rows of the solder balls 6. In the embodiment shown in FIG. 2, the bonding pads 12 are provided in a single row between the first and second rows of the electrode patterns 10. Therefore, the interconnection patterns 13 connecting the electrode patterns 10 and the bonding pads 12 are provided in such a manner that they are threaded between the electrode patterns 10.
However, along with a rapid chip shrink (i.e., minimization) of the semiconductor chip 4, there is a tendency that a pitch of the electrode pads 5 is reduced resulting in a reduction of the distance between the neighboring wires 14. This causes a problem that the wires are short-circuited due to wire flow.
Also, in order to meet requirements related to the above-described structures, recent semiconductor device structures utilize structures in which the solder balls 6 and the electrode patterns 10 are also provided on the lower part of the semiconductor chip 4.
With such structures in which the electrode patterns 10 are provided adjacent to the semiconductor chip 4, the bonding pads 12 and the electrode pads 10 may be separated from each other. Thus, the tape 2 may be provided with an increased number of interconnection patterns 13 formed thereon.
However, with the fine-pitched structure, since the distance between neighboring electrode patterns 10 is reduced, the interconnection patterns 13 on the tape 2 will also be fine. Therefore, a patterning will be difficult to implement and can result in a reduction in a yield during a manufacturing process.